Various types of synchronous oscillation circuits have been proposed, which generate a synchronizing signal shaping a sawtooth waveform or a triangular waveform for use in a so-called PWM (Pulse Width Modulation) circuit.
When employed as a power source IC of a digital machine, the above synchronous oscillation circuit normally operates in synchronous oscillation by using a signal in sync with an operating clock of a microcomputer provided in the machine as a synchronizing pulse. However, the synchronous oscillation circuit operates in self-advancing oscillation when the operating clock is not supplied stably, for example, at power-up.
FIG. 8 shows an example arrangement of the above synchronous oscillation circuit (Prior Art 1), and FIG. 9 shows a time chart to explain an operation of the circuit illustrated in FIG. 8.
As show n in FIG. 8, the synchronous oscillation circuit comprises a time constant means 51, a first voltage generating means 52, a second voltage generating means 53, a first comparing means 54, a second comparing means 55 a state maintaining means 56, and a logical OR circuit 57. The time constant means 51 raises or drops a voltage V0 (hereinafter, referred to simply as V0) over time. The first voltage generating means 52 generates a constant voltage V1 (hereinafter, referred to simply as V1), and the second voltage generating means 53 generates a constant voltage V2 (hereinafter, referred to simply as V2) which is lower than V1. The first comparing means 54 compares V0 with V1, and the second comparing means 55 compares V0 with V2. The state maintaining means 56 maintains a rising or dropping state of V0. The logical OR circuit 57 provides the state maintaining means 56 with a logical OR of an output from the second comparing means 55 and the synchronizing pulse.
Assume that the synchronizing pulse is in the LOW level (hereinafter, referred to simply as L), and V0 outputted from the time constant means 51 is rising at power-up as is shown at the top row in FIG. 9. Under these conditions, V0 keeps rising over time until it reaches V1, whereupon an output VH (hereinafter, referred to simply as VH) of the first comparing means 54 shifts to a HIGH level (hereinafter, referred to simply as H). Hence, an output of the state maintaining means 56 inverts, whereupon V0 starts to drop with the action of the time constant means 51. This dropping state of V0 is maintained by the state maintaining means 56 after VH has shifted to L due to the dropping of V0. When V0 drops as low as V2, an output VL (hereinafter, referred to simply as VL) of the second comparing means 55 shifts to H, and so does an output of the logical OR circuit 57. Hence, the state of the state maintaining means 56 inverts, whereupon V0 starts to rise again. By periodically repeating the above action, the circuit operates in the self-advancing oscillation, and in the meantime, V0 shapes a triangular waveform or a sawtooth waveform by rising to V1 and dropping to V2 repetitively.
Upon receipt of a synchronizing pulse having a cycle shorter than that of the self-advancing oscillation as shown at the bottom row in FIG. 9, the circuit starts to operate in the following manner. That is, as shown at the middle row in FIG. 9, an output from the logical OR circuit 57 shifts to H at the instant the synchronizing pulse shifts to H. Hence, the state of the state maintaining means 56 inverts, whereupon V0 starts to rise in sync with the rising-up of the synchronizing pulse. When V0 reaches V1, the state of the state maintaining means 56 inverts again, whereupon V0 starts to drop. Then, the state maintaining means 56 inverts its state again upon input of the following synchronizing pulse, whereupon V0 starts to rise again. By periodically repeating the above action, the circuit operates in the synchronous oscillation in sync with the synchronizing signal.
As previously mentioned, when employed as a power source IC of a digital machine, the synchronous oscillation circuit normally operates in the synchronous oscillation, and when the operating clock is not supplied stably, it operates in the self-advancing oscillation. Therefore, in order to stabilize the power source, it is ideal that the cycle of the synchronous oscillation is equal to that of the self-advancing oscillation.
In the conventional synchronous oscillation circuit described above, if the cycle of the synchronizing pulse is longer than that of the self -advancing oscillation, VL of the second comparing means 55 shifts to H before the synchronizing pulse does so, and the state of the state maintaining means 56 inverts at this shifting, thereby making normal synchronous oscillation impossible, For this reason, the cycle of the synchronizing pulse has to be shorter than that of the self-advancing oscillation. As a result, the oscillation cycle becomes shorter in the synchronous oscillation than in the self-advancing oscillation, and so does the oscillation amplitude.
The above problem is solved by the disclosure in Japanese Laid-Open Patent Application No. 216605/1989 (Japanese Official Gazette, Tokukaihei No. 1-2166605, Publishing Date: Aug. 30, 1989) (Prior Art 2). To be more specific, with the use of the arrangement of FIG. 8, a synchronizing pulse detecting circuit detects the absence or presence of the synchronizing pulse, and upon detection of the synchronizing pulse, V2 is dropped. Consequently, VL of the second comparing means 55 is nullified, thereby making the oscillation cycle and oscillation amplitude in the synchronous oscillation equal to those in the self-advancing oscillation.
In case that an oscillation waveform is a sawtooth waveform with a short rising period, if the synchronizing pulse has a large duty ratio, the timing of the falling edge of the synchronizing pulse comes after the peak timing of the oscillation waveform. Hence, two inputs, each assigning a conflicting function to the state maintaining means 56, compete against each other, thereby making normal oscillation impossible. For this reason, the duty ratio of the synchronizing pulse has be adequately small.
The synchronizing pulse shifts repetitively between H and L. Thus, according to the technique disclosed in aforementioned Japanese Laid-Open Patent Application No. 216605/1989, the synchronizing pulse detecting circuit has to confirm whether or not the synchronizing pulse has remained in L for a predetermined time before it detects the absence of the synchronizing pulse. Under these conditions, even though the synchronizing signal has been actually absent, VL of the second comparing means 55 is kept nullified until the absence of the synchronizing signal is confirmed. Hence, V0 as an oscillation output drops temporarily far below V2 which is the lower limit in the requirements, thereby causing problematic variance in oscillation amplitude.
Also, V2 is often grounded through a capacitor so as not to vary with a noise or interference with other circuits. Under these conditions, however, once V2 is lowered to nullify VL of the second comparing means 55, it takes a considerable time until V2 has been restored to the original voltage since the nullification is cancelled due to the absence of the synchronizing pulse. Consequently, the circuit can not smoothly shift to the self-advancing oscillation from the synchronous oscillation, and the oscillation cycle and oscillation amplitude remain unstable until the shifting is completed.